The present invention relates in a general level to techniques of manufacturing aspects of dopant doped silicon layers and a method for producing such doped layers. In more particularly, the present invention is concerned with a chemical vapor deposition (CVD) method for producing silicon layers doped with a dopant. The present invention relates also to an arrangement for manufacturing dopant doped silicon layers. The invention concerns several aspects. A first aspect of the invention concerns a growing process of dopant doped epitaxial silicon or polycrystalline silicon layers according to the preamble of an independent claim thereof. A second aspect of the invention concerns an arrangement according to the preamble of an independent claim thereof. A third aspect of the invention concerns a method of growing dopant doped silicon layer according to the preamble of an independent claim thereof. A fourth aspect of the invention concerns a use of halide as a precursor according to the preamble of an independent claim thereof. A fifth aspect of the invention concerns a surface structure according to the preamble of an independent claim thereof. A sixth aspect of the invention concerns a wafer according to an independent claim thereof.
For the sake of clarity, in the following the word “dopant” has been used to refer also to other elements than 3rd group or 5th group elements. In particular, dopant should be understood as a substance to be doped into a substrate and/or into a carrier matrix substance, including also the very high dopant concentrations of known CVD processes. In general if not otherwise indicated for a dopant, dopant concentration in a doped structure is smaller than that of the carrier matrix forming substance.
A CVD process basics has been known as such from its thousands of variants, for a long time for those skilled in the art. In the semi-conductor industry in a known process, layers are grown from the vapour phase on a substrate.
A surface structure on a wafer, for instance, can be grown as film layers with advantageous dopants, and/or etched away in order to have certain surface structure in a physical and/or compositional appearance. Such structure may serve as a key to gain certain optical, mechanical properties of the layers and/or electrical properties.
In certain fields of technology, in semi-conductor manufacturing for instance, the quality requirements of the substrate are very high for a certain composition of the surface layer for a specified application. In such a case it is crucial for the manufacturing process to minimize potential defects caused by contamination. In particular, this applies to surface defects such as particles, mounds, stacking faults, spikes and other defects known in the art.
Thin silicon layers which have properties different from those of the single crystal silicon substrate are commonly used for the processing of many types of semi-conductor devices and circuits. Such layers are typically between 0.1 μm and 100 μm thick but can be even thicker than 100 μm or thinner than 0.1 μm. The layers can be epitaxial, that is single crystalline, when grown on silicon; or they can be polycrystalline or amorphous when grown on a suitable intermediate layer, for instance an oxide or nitride layer. Instead of a single layer also multiple layers, either epitaxial, polycrystalline or amorphous, can be grown on top of each other as such, as known from the known techniques. If the layers are thin, low temperature deposition processes well below 1050° C. can be used. If the layers are thick, however, for instance over 1 μm or even over 10 μm, the deposition rate becomes important due to its effect on the throughput of the deposition equipment. For the deposition of such thick silicon layers high temperature CVD is commonly used.
A known CVD reactor comprises a quartz chamber. The word quartz here refers to any known reactor material of the chamber, comprising silica, suitable for CVD, irrespective on the actual reactor or the chamber material composition. The chamber is heated either with infrared and/or visible radiation, or by radio frequency (RF) radiation, induction based heating, or by combination of these. The heating affects directly mainly either the silicon wafer or the susceptor on which the wafer rests during the processing. Clean quartz does not absorb RF-radiation to any significant degree. However, quartz absorbs light and absorbs infrared radiation quite significantly. In addition, heat is transferred to the quartz walls due to absorption in silicon deposits on the quartz, or radiation and conduction from the substrate and susceptor. Therefore, the quartz wall of the reactor becomes quite hot during the CVD process.
A known CVD process utilises silicon containing source gas mixed with either an inert or a reducing carrier gas. Usually hydrogen (H2) is used as a carrier gas and silicon hydrides (i.e. silane SiH4), silicon chlorides (i.e. silicon tetrachloride SiCl4,) or chlorosilicon hydrides, i.e. dichlorosilane (DCS, SiH2Cl2) or trichlorosilane (TCS, SiHCl3) as silicon source gases. At high temperatures, above about 1100° C., the CVD processes can be capable of very high deposition rates of up to or over 5 μm/min depending on the design of the reactor, gas flow rates, temperature and pressure. In particular, relatively thick epitaxial and polycrystalline silicon layers are usually deposited using a high temperature of between 1050° C. and 1200° C. and either silicon tetrachloride or trichlorosilane as the source gas.
Epitaxial or polycrystalline silicon layers deposited using a known CVD can be doped substitutionally with impurity atoms to achieve suitable electrical or other properties of the resulting alloy. In particular, the conductivity of the layer can be adjusted with the dopants boron for p-type layers and arsenic, phosphorus or antimony for n-type layers. In addition, silicon can also be doped substitutionally and isoelectronically, i.e. without affecting the electrical conductivity, with the elements germanium and carbon. Typically used source gases for the dopants in such a CVD process are hydrides, for instance diborane, (B2H6) for boron; arsine (AsH3) for arsenic, phosphine (PH3) for phosphorus and germane (germanium tetrahydride, GeH4) for germanium. Typical electrically active dopant atom concentrations in the grown layers are between 1013 cm−3 and 1019 cm−3. Both higher and lower concentrations are possible and also fairly commonly used. In particular highly boron doped p-type epitaxial layers with high boron concentrations of between 1·1019 cm−3 and 2·1020 cm−3 are quite commonly used because they exhibit a very low etch rate compared to moderately doped silicon when alkaline wet etchants, for instance potassium hydroxide (KOH), are used. Therefore, a highly boron doped layer can function as an effective etch stop in the wet etching of silicon. Such an etch stop layer can be used for instance for the fabrication of silicon micromechanical structures, comprising freestanding silicon membranes.
The heavily boron doped etch stop layer can form the freestanding silicon membrane. More often, however, the highly boron doped layer is used in a double layer structure in which the thin, highly doped p-type layer is covered with a moderately doped layer. Such a structure is used in known techniques to fabricate a silicon membrane from the upper layer which can be doped to a different concentration of either n- or p-type dopant. In such a case, the silicon substrate is first removed from the desired areas for instance with a combination of grinding and wet etching with an alkaline etchant. Thereafter the boron doped etch stop layer is removed with a suitable etchant to leave the surface structure formed by the moderately doped top silicon layer.
When silicon is doped according to the known techniques, to a concentration over 1·1020 cm−3 with boron, significant tensile stress results in such a doped layer due to the small size of the boron atom. This tensile stress causes wafer warpage and generally also a network of misfit dislocations and associated surface defects in the layer. Wafer warpage, surface defects and misfit dislocations can have undesirable effects on subsequent device processing and the properties of devices processed on such wafers. For this reason highly boron doped CVD-grown layers are usually counterdoped with germanium to prevent excessive stress in the layer. Stress compensation is due to the Ge atom being larger than B. In the CVD process germane (GeH4) is commonly used as the germanium source gas either as a pure gas or more commonly in a dilute mixture with hydrogen. The desirable germanium concentration for stress compensation in the grown layer is approximately 6 times the concentration of boron. In addition to stress compensation Ge doping can also be used to modify the electronic band structure of silicon. For such purposes the germanium concentration in the SiGe alloy can be up to 20%, 30% or even higher. Recently Ge doping has also been used to create substrates for thin layers of strained silicon. In this application a relative thick layer of compositionally graded SiGe is grown on the silicon substrate. The layer is grown sufficiently thick, typically 1 to 3 μm, for the stress in the layer to become almost completely relaxed due to the formation of a dislocation network. When a thin layer of silicon is then grown on the relaxed SiGe-layer, the electronic band structure of the silicon layer is affected by the large tensile strain caused by the relatively large lattice constant of the relaxed SiGe, affecting the mobility of charge carriers in a beneficial way.
Another use of isoelectronic doping is to use carbon. Carbon is only soluble in silicon as estimated up to concentrations of perhaps 1-2%, depending on the temperature. However, carbon can still have a major effect on the electronic band gap properties of silicon. In addition, carbon tends to prevent the diffusion of boron at high temperatures, making it possible to achieve more abrupt interfaces between highly boron doped and moderately doped silicon layers.
Hydrides such as germane and diborane are easily decomposed at elevated temperatures leading to significant coating of the quartz chamber walls with dark deposits. These deposits increase the absorption of radiation by the quartz chamber and lead to a further increase in the quartz temperature. Furthermore, boron can react with quartz at high temperatures causing high stresses in the quartz chamber walls, which may eventually cause the chamber to crack. As a result, in the known techniques, the highly doped silicon layers are usually deposited at a relatively low temperature, usually around 1000° C. for heavily boron doped layers, or at even much lower temperatures for SiGe and carbon doped silicon.
In a known process Si2H2Cl2 dichlorosilane or SiH4 silane are usually used as the source gas in low temperatures for keeping the deposition rates in acceptable level. In addition, in spite of the lower process temperature the quartz chamber still becomes coated with deposits, which need to be removed with long etching processes using a suitable gaseous cleaning agent such as hydrogen chloride (HCl). Both the low deposition rate and the long etching times of known techniques reduce the throughput of the CVD equipment and thus increasing the cost of depositing the highly doped layers. In addition, both dichlorosilane, silane and germane gases are very expensive further increasing the cost.
Surface defects created during epitaxy tend to be detrimental for subsequent device processing done on epitaxial wafers. Wafer bonding is particularly sensitive to such defects. Typically the height of the epitaxial surface defects is proportional to the thickness of the epitaxial layer. Therefore, surface defects tend to be much more detrimental on thick epitaxial layers than on thin layers. Surface defects are usually caused by foreign material on the substrate surface, for instance a particle or an oxide island. Oxide islands have a greater tendency to form at low temperatures where the reducing hydrogen atmosphere is less effective in preventing their formation. In addition, easily decomposable gases such as hydrides have a tendency to react in the gas phase of the epitaxial reactor, thus forming small particles which can then induce the formation of surface defects. An additional source of particles in the CVD reactor is the undesirable deposits formed on the quartz walls.
FIG. 1A demonstrates a known CVD-process as such having duration from the beginning (0) to moment n demonstrated on the horizontal time axis, however the moments and units are indicated in arbitrary units, just for a demonstrative purposes. The substrate is transferred into the reactor chamber at the beginning of the process at a starting temperature indicated by the word “Start” in the figure. The substrate is heated from beginning to a moment of time kn1 in a H2 atmosphere as preparing for removing an oxide layer from the surface between moments kn2 and kn1, in an elevated temperature T. This is indicated in the figure by the word “Bake”. When the oxide from the substrate surface is removed, the process temperature is changed at kn2 corresponding the conditions of the deposition of the doped layer. The layer is grown during a time interval from moment kn2 to a moment kn3. It is demonstrated in the figure, to be done in an H2 atmosphere and by using GeH4 as the germanium source and SiH2Cl2 (DCS) as silicon source. When the necessary layer thickness is achieved, the feed of the source gases is stopped. The temperature is lowered at a moment of time kn3; the substrate is cooled whilst maintaining the carrier gas flow through the chamber. After the temperature has been lowered sufficiently, for instance to or below about 900° C., the substrate with the layer is taken away from the reactor. Following the removal of the substrate the reactor is heated rapidly to a suitably high temperature, for example around 1200° C. to heat the chamber walls for removing the undesirable deposits with a gaseous etchant. At the moment kn4 the etching of the CVD-chamber, the reactor, begins, and continues to a moment kn5. After the moment kn5 the reactor is ready for depositing the next layer. Etching is indicated in FIG. 1A to be done by HCl as an etchant, but other kind of etchants can be used as well depending on the known process detail.
In FIG. 1A, in order to get a sufficient layer structure thickness in a low temperature T the deposition time kn3-kn2 for the doped layer on the substrate is a quite long and occurrence probability of particles is also quite high. Especially because of the thermal decomposition properties of the precursors and also because long times allow also slower reactions to occur and may lead to particle formation in the reaction chamber, not only in the volume but also on the inner surfaces of the chamber, and the substrate still being therein.
In FIG. 1A in the etching phase the etching time kn5-kn4 is aimed to remove all kinds of deposits from the empty reactor in an elevated temperature. During that phase quite a lot of chemicals are removed from the chamber, more or less as waste. For sufficient cleanliness for a next substrate, the etching time should be long enough, and generally the interval kn3-kn2 should be proportional to interval kn5-kn4. Consequently, much of chemicals are wasted if compared to their amount on the substrate surface and the known process occurs relatively slowly.
Thus, there is a need for a faster, cleaner and cheaper CVD process for depositing highly doped, thick silicon layers of high surface perfection.